Technical Field
The disclosure in generally relates to a semiconductor device and a method for fabricating the same, and more particularly to a three dimension (3D) memory device and a method for fabricating the same.
Description of the Related Art
Non-volatile memory (NVM) device which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell has been widely adopted by bulk solid state memory applications in portable audiovisual entertainment devices, cell phones or digital cameras etc. Recently, various three dimensional (3D) flash memory device, such as a vertical-channel (VC) 3D NAND flash memory device that has a multi-layers stacking structure, may possess a higher density memory and excellent electrical characteristics, e.g. reliability in data storage and high operating speed.
A 3D NVM device typically comprises a multi-layers stacking structure constituted by a plurality of insulation layers and a plurality of conductive layers alternatively stacked with each other. FIG. 1 is a cross-sectional view illustrating a multi-layers stacking structure 100 of a 3D NVM device in accordance with prior art. The multi-layers stacking structure 100 comprises a trench 101 used to divide the multi-layers stacking structure 100 into a plurality of ridge-shaped stacks 102 each of which comprises a plurality of conductive stripes 102a formed by the patterned conductive layers. The 3D NVM device further comprises a memory layer 103 and channel layer 104, wherein the memory layer 103 is disposed on sidewalls of the trench; the channel layer 104 covers on the ridge-shaped stacks 102 and the channel layer 104; and a plurality of memory cells 105 are defined at the positions where the conductive stripes 102a, the memory layer 103 and the channel layer 104 intersected with each other. The memory cells 105 that are electrically connected in series to form a vertical string electrical connection by the channel layer 104 are electrically connected to a corresponding bit line (not shown) through a metal contact 106 formed on the channel layer 104 overlaid on the ridge-shaped stacks 102.
In order to control the memory cells 105 more effectively, a thinner thickness of the channel layer 104 is required and the process window for forming the metal contact 106 on the channel layer 104 may be rather limited (or even not enough). Furthermore, a silicide layer (not shown) may be formed on the interface between a barrier layer of the metal contact 106 and the channel layer 104 that is typically made of poly silicon, and voids may easily occurs in the silicide layer due to thinner thickness of the channel layer 104. As a result the contact resistance of the metal contact 106 and the channel layer 104 may be increased significantly.
Therefore, there is a need of providing an improved memory device and a method for fabricating the same to obviate the drawbacks encountered from the prior art.